Phase locked loops (or PLLs) are used to generate an output signal with a defined phase and frequency relationship to an input reference signal. The output signal is matched to the phase of the input reference signal by a feedback loop in which the phase difference between the input reference signal and the output signal is determined by a phase detector. In a digital phase locked loop, the phase detector outputs a digital signal. The output from the phase detector (indicating phase error) is received by a loop filter. The loop filter in turn provides an output signal to a frequency controlled oscillator. In an all-digital phase locked loop, the phase detector may output a digital signal, the loop filter may be a digital loop filter, and the frequency controlled oscillator may be a digitally controlled oscillator.
Phase locked loops may operate in a linear mode, in which the phase detector provides a signal that varies in a linear relationship with the phase error. A phase locked loop may also operate in a “bang-bang” mode, in which the phase detector provides a binary signal, indicating only that the phase error is positive or negative.
It is often desirable to know whether a PLL has achieved phase lock. For instance, in the context of a PLL being used to generate a local oscillator (LO) signal for a tuner, it is desirable to know if and when the PLL reaches a locked state after a tuning action. It is further desirable to know when the system is out of lock, for example, due to temperature drift or an unsuccessful tuning action.